(1) Field of the Invention
The present invention relates to a method used to create a capacitor structure for a dynamic random access memory, (DRAM) device.
(2) Description of the Prior Art
The semiconductor industry is continually striving to improve semiconductor device performance, while still attempting to reduce the manufacturing costs of these semiconductor devices. These objectives have been in part realized by the ability of the semiconductor industry to fabricate semiconductor memory chips using sub-micron features. The use of sub-micron features, or micro-miniaturization, results in a reduction of performance degrading capacitances and resistances. In addition, the use of smaller features results in a smaller chip, however still possessing the same level of integration obtained for larger semiconductor chips fabricated with larger features. This allows a greater number of the denser, smaller chips to be obtained from a specific size starting substrate, thus resulting in a lower manufacturing cost for an individual chip.
The use of smaller, or sub-micron, features, when used for the fabrication of dynamic random access memory (DRAM) devices, in which the capacitor of the DRAM device is a crown or stacked capacitor (STC) structure, presents difficulties when attempting to increase STC capacitance. A DRAM cell is usually comprised of the crown/STC structure overlying a transfer gate transistor, and connected to the source of the transfer gate transistor. However, the decreasing size of the transfer gate transistor limits the dimensions of the crown/STC structure. To increase the capacitance of the crown/STC structure, comprised of two electrodes, separated by a dielectric layer, either the thickness of the dielectric layer has to be decreased, or the area of the capacitor has to be increased. The reduction in dielectric thickness is limited by increasing reliability and yield risks, encountered with ultra thin dielectric layers. In addition the area of the crown/STC structure is limited by the area of the underlying transfer gate transistor dimensions. The advancement of the DRAM technology to densities of 256 million cells per chip, or greater, has resulted in a specific cell in which a smaller transfer gate transistor is being used, resulting in less of an overlying area available for placement of overlying crown/STC structures.
One method of maintaining, or increasing crown/STC capacitance, while still decreasing the lateral dimension of the capacitor, has been the use of rough, or hemispherical grain (HSG) silicon layers. The use of HSG silicon, comprised of convex and concave features, results in an increase in surface area when compared to counterparts fabricated with smooth, polysilicon surfaces. One factor influencing HSG silicon growth is the dopant concentration of the underlying amorphous silicon or polysilicon layer, from which the HSG silicon layer is formed from. To enhance DRAM performance, the capacitance depletion characteristics of the storage node structure has to be minimized, accomplished via the use of a heavily doped storage node structure. However, to obtain maximum HSG silicon roughness, the doping level of the underlying material, from which the HSG silicon layer is formed on, has to be maintained at a low level. Therefore to optimize these parameters, capacitance depletion and HSG silicon roughness, a novel method, incorporating a combination of doped and undoped silicon layers, is used as a buffer layer, in the formation of the HSG silicon layer, and is described in this invention. Prior art, such as Ping et al, in U.S. Pat. No. 5,691,228, describe a method for growing HSG silicon layers, however that method does not include the novel combination of silicon layers, and seeding/anneal steps, used in this present invention, allowing HSG silicon layers to be formed from underlying undoped layers, while maintaining a high dopant level for the storage node structure.